Phase-Locked Loop

This example shows a simple synchronous-reference-frame phase-locked loop for a three-phase voltage system.

The objective is to estimate the grid angle theta_hat so the measured voltage vector aligns with the rotating d-axis. In the locked state, the q-axis voltage is driven toward zero:

\[ v_q \rightarrow 0 \]

The estimated angle is fed back into the abc -> dq transformation. A PI controller acts on the q-axis phase error and corrects the estimated angular frequency. The angle output is shown as a phasor-style gain/normalization block rather than a software-like modulo function, because this diagram is meant to read as an s-domain control schematic.

Block Diagram

TikZ/LaTeX source: phase-locked-loop-dq.tex

Signal Meaning

Signal	Meaning
v_a, v_b, v_c	measured three-phase voltages
theta_hat	estimated electrical grid angle
v_d, v_q	voltage components in the estimated rotating dq frame
e_pll	phase detector error, usually derived from v_q
delta_omega	frequency correction from the PI controller
omega_hat	estimated angular frequency

Notes

This is a conceptual control-theory diagram. A production PLL normally adds filtering, voltage magnitude supervision, frequency limits, anti-windup, startup handling, and fault behavior for weak-grid or unbalanced-voltage conditions.

For control-theory block diagrams, TikZ/LaTeX is preferred over PlantUML because it supports mathematical notation, summing junctions, transfer functions, and precise signal-flow layout. PlantUML remains useful for architecture, workflows, state machines, and linked system diagrams.